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MC74VHCT74A Dual D-Type Flip-Flop with Set and Reset
The MC74VHCT74A is an advanced high speed CMOS D-type flip-flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The signal level applied to the D input is transferred to Q output during the positive going transition of the Clock pulse. Reset (RD) and Set (SD) are independent of the Clock (CP) and are accomplished by setting the appropriate input Low. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings. The VHCT74A input structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc.
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14 SOIC-14 D SUFFIX CASE 751A 1 14 TSSOP-14 DT SUFFIX CASE 948G VHCT 74A ALYWG G VHCT74AG AWLYWW
1
1
A = Assembly Location 1 WL, L = Wafer Lot Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) RD1 D1 CP1 SD1 Q1 Q1 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RD2 D2 CP2 SD2 Q2 Q2
* * * * * * * * * * *
High Speed: fmax = 60 MHz (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 4.5 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 128 FETs or 32 Equivalent Gates Pb-Free Packages are Available
Figure 1. Pin Assignment FUNCTION TABLE
Inputs SD L H L H H H H H RD H L L H H H H H CP X X X D X X X H L X X X Outputs Q Q H L L H H* H* H L L H No Change No Change No Change
RD1 D1 CP1 SD1
1 2 3 4 5 6 Q1 Q1
RD2 D2 CP2 SD2
13 12 11 10 9 8 Q2 Q2
L H
Figure 2. Logic Diagram
*Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously.
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
1
July, 2006 - Rev. 5
Publication Order Number: MC74VHCT74A/D
MC74VHCT74A
III I I II I I I IIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I II I I I I II I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I II I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I III I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII
II I I I IIIIIIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I IIII IIIIIIIIIIIIIIIIIIIIIII IIIIII
MAXIMUM RATINGS
SymbolIIIIIIIIIIIIII Parameter VCC Vin DC Supply Voltage DC Input Voltage Value Unit V V V -0.5 to + 7.0 -0.5 to + 7.0 Vout IIK DC Output Voltage VCC = 0 High or Low State Input Diode Current -0.5 to + 7.0 -0.5 to VCC + 0.5 -20 20 25 50 mA mA mA mA IOK Iout Output Diode Current (VOUT < GND; VOUT > VCC) DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package 500 450 mW C Tstg -65 to + 150 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating - SOIC Packages: - 7 mW/C from 65 to 125C TSSOP Package: - 6.1 mW/C from 65 to 125C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin
Parameter
Min 4.5 0 0 0
Max 5.5 5.5
Unit V V V
DC Supply Voltage DC Input Voltage
Vout TA
DC Output Voltage VCC = 0 High or Low State Operating Temperature
5.5 VCC
-40 0
+ 85 20
C
tr, tf
Input Rise and Fall Time
VCC =5.0 V 0.5 V
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol VIH VIL
Parameter
Test Conditions
VCC V
TA = 25C Typ
TA = - 40 to 85C Min 2.0 Max
Min 2.0
Max
Unit V V V
Minimum High-Level Input Voltage
4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5
Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Vin = VIH or VIL
0.8
0.8
VOH
IOH = -50 mA IOH = -8 mA IOL = 50 mA IOL = 8 mA
4.4
4.5
4.4
3.94
3.80
VOL
Maximum Low-Level Output Voltage Vin = VIH or VIL
0.0
0.1
0.1
V
0.36 0.1 2.0
0.44 1.0
Iin
Maximum Input Leakage Current
Vin = 5.5 V or GND Vin = VCC or GND
0 to 5.5 5.5 5.5 0
mA mA
ICC
Maximum Quiescent Supply Current Quiescent Supply Current Output Leakage Current
20.0 1.50 5.0
ICCT
Per Input: VIN = 3.4 V Other Input: VCC or GND VOUT = 5.5 V
1.35 0.5
mA mA
IOPD
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MC74VHCT74A
III I I I I I II III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIII I I I I IIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIII II I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIII I I I I II I I I IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol tPLH, tPHL tPLH, tPHL fmax Cin Parameter TA = 25C Typ 5.8 6.3 7.6 8.1 TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 80 65 Max 9.0 10.0 Test Conditions Min Max 7.8 8.8 Unit ns ns Maximum Propagation Delay, CP to Q or Q Maximum Propagation Delay, SD or RD to Q or Q Maximum Clock Frequency (50% Duty Cycle) VCC = 5.0 0.5V VCC = 5.0 0.5V VCC = 5.0 0.5V CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 10.4 11.4 12.0 13.0 100 80 160 140 4 MHz pF Maximum Input Capacitance 10 10 Typical @ 25C, VCC = 5.0 V 24 CPD Power Dissipation Capacitance (Note 1) pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 2 (per flip-flop). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
TIMING REQUIREMENTS (Input tr = tf = 3.0 ns)
IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIII I IIIII I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII
Symbol tw tw Parameter VCC V Guaranteed Limit TA = 25C 5.0 5.0 5.0 0.0 3.5 TA = - 40 to 85C 5.0 5.0 5.0 0.0 3.5 Unit ns ns ns ns ns Minimum Pulse Width, CP 5.0 0.5 5.0 0.5 5.0 0.5 5.0 0.5 5.0 0.5 Minimum Pulse Width, RD or SD Minimum Setup Time, D to CP Minimum Hold Time, D to CP tsu th trec Minimum Recovery Time, SD or RD to CP
ORDERING INFORMATION
Device MC74VHCT74AD MC74VHCT74ADR2 MC74VHCT74ADR2G MC74VHCT74ADT MC74VHCT74ADTR2 MC74VHCT74ADTR2G Package SOIC-14 SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* TSSOP-14* Shipping 55 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 96 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74VHCT74A
tw 3V 1.5 V tw 1/fmax tPLH Q or Q 1.5 V tPHL VOH VOL CP Q or Q GND SD or RD 1.5 V tPHL Q or Q 1.5V VCC tPLH 1.5V VCC trec 1.5V 3V GND 3V GND 3V GND
CP
Figure 3. Switching Waveform
Figure 4. Switching Waveform
TEST POINT VALID D 1.5 V tsu th 1.5 V 3V GND 3V GND *Includes all probe and jig capacitance OUTPUT DEVICE UNDER TEST C L*
CP
Figure 5. Switching Waveform
Figure 6. Switching Waveform
INPUT
Figure 7. Input Equivalent Circuit
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MC74VHCT74A
PACKAGE DIMENSIONS
SOIC-14 D SUFFIX CASE 751A-03 ISSUE G
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G C
R X 45 _
F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
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MC74VHCT74A
PACKAGE DIMENSIONS
TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE A
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 --- 1.20 --- 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
DIM A B C D F G H J J1 K K1 L M
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC74VHCT74A/D

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